1. Field of the Invention
This invention related to a nonvolatile memory circuit device having nonvolatile transistors as memory cells.
2. Description of the Related Art
As the memory cells of the nonvolatile memory circuit device have been miniaturized, it becomes highly possible that the memory cell will be damaged or data will be erroneously programmed when a power source voltage is applied to the drain of the memory cell as it is in the data readout mode. For this reason, it is required to suppress the drain voltage of the memory cell to a certain low voltage level during the data readout mode of the memory circuit of this type, and at the same time it is necessary to attain the highly reliable readout operation.
FIG. 1 is a circuit diagram showing the circuit construction of a conventional nonvolatile memory circuit device. To simplify the explanation, a data writing or programming circuit and the related circuits are omitted. As shown in FIG. 1, intermediate potential output circuit 30 for supplying a potential lower than potential Vcc is connected between positive power source potential terminal Vcc and node A. A plurality of column selection transistors 31 are commonly connected at one end to node A and respectively connected at the other end to bit lines 32. A plurality of word lines 33 are arranged to intersect bit lines 32, and memory cells 34 formed of nonvolatile transistors are arranged in respective positions in which the bit lines and word lines intersect each other. The drains of those memory cells which lie on the same column are connected to a corresponding one of bit lines 32 and the gates of those memory cells which lie on the same row are connected to a corresponding one of word lines 33. The sources of the memory cells are connected to ground potential terminal Vss. Further, sense amplifier 35 formed of a voltage comparator having an analog circuit structure is connected to node A. Reference potential Vref which is slightly lower than the output potential of intermediate potential output circuit 30 is supplied to sense amplifier 35 which in turn compares the potential at node A with reference potential Vref to output data Dout corresponding to the comparison result.
In a memory circuit of the above construction, the potential at node A is always kept at a potential level lower than power source potential Vcc by means of intermediate potential output circuit 30. As a result, the lower potential is supplied to the drain of a memory cell selected in the data readout mode, and therefore the above-described problems of damage of the memory cell and erroneous programming operation can be solved.
However, the amplitude of the potential at node A is limited by the presence of intermediate potential output circuit 30, and it is required to use a voltage comparator type sense amplifier with complicated analog circuit construction as sense amplifier 35. Such a sense amplifier has the disadvantages that the power source voltage margin is reduced, a low voltage operation is difficult and the current consumption is large.
Further, when memory cell 34 selected in the data readout mode is turned on, a D.C. penetration current flows between power source potential terminal Vcc and ground potential terminal Vss, further increasing the current consumption. In addition, intermediate potential output circuit 30 is required to have a large current capacity and consequently the circuit construction thereof becomes complex.
As described above, since, in the conventional nonvolatile memory circuit device, the potential to be detected by the sense amplifier is set at a low level to prevent damage of the memory cell and erroneous programming operation, there arise problems that it cannot be driven at a low voltage and the current consumption becomes large.